utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co., ltd. 1 qw-r103-002,b current mode pwm control circuits description the utc uc3842a/3843a provide the necessary functions to implement off-line or dc to dc fixed frequency current mode , controlled switching circuits with a minimal external part count features *low external part count. *low start up current ( typical 0.12ma ) *automatic feed forward compensation *pulse-by-pulse current limiting *under-voltage lockout with hysteresis *double pulse suppression *high current totem pole output to drive mosfet directly *internally trimmed band gap reference *500khz operation dip-8 sop-8 block diagram 7 5 7 6 5 4 3 1 2 8 internal bias 5v ref s/r u.v.l.o r s pwm latch vref good logic error amplifier 1/2vref 1/3vref 1v oscillator vref vfb comp current sense rt/ct vcc gnd output vcc gnd current sense comparator absolute maximum ratings (ta=25 c) parameter symbol value unit supply voltage(low impedance source) v cc 30 v supply voltage(icc<30ma) vcc self limiting v output current ( peak ) io +-1 a output energy(capacity load) 5 j analog inputs(pin 2,3) v i(ana) -0.3 ~ +6.3 v error amplifier output sink current i sink(ea) 10 ma power dissipation pd dip-8 at t amb <=25 c 1.0 w sop-8 at t amb <=25 c 0.5 w lead temperature( soldering 10 sec ) tlead 300 c datasheet.in
utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co., ltd. 2 qw-r103-002,b (continued) parameter symbol value unit storage temperature tstg -65 ~ +150 c operating junction temperature tj +150 c note 1: ta>25 c, p d derated with 8mw/ c. electrical characteristics (0 c <=ta<=70 c,v cc =15v,r t =10k ? ,c t =3.3nf,unless otherwise specified) parameter symbol test conditions min typ max unit reference section output voltage v ref tj=25 c,io=1ma 4.9 5 5.1 v line regulation ? v ref 12<=v in <=25v 6 20 mv load regulation ? v ref 1<=io=20ma 6 25 mv temperature stability (note 2) 0.2 0.4 mv/ c total output variation line, load, temp(note 2) 4.82 5.18 v output noise voltage vosc 10hz<=f<=10khz,tj=25 c (note 2) 50 uv long term stability ta=25 c,1000hrs(note 2) 5 25 mv output short circuit i sc -30 -100 -180 ma oscillator section initial accuracy f tj=25 c 47 52 57 khz voltage stability ? f/ ? vcc 12<=vcc<=25v 0.2 1 % temperature stability tmin<=t a <=tmax(note 2) 5 % amplitude vosc vpin 4 peak to peak 1.7 v error amplifier section input voltage v i(ea) vpin 1=2.5v 2.42 2.50 2.58 v input bias current i bias -0.3 -2 a a vol 2 <=vo<=4v 60 90 db unity gain bandwidth tj=25 c (note 2) 0.7 1 mhz psrr i2<=vcc<=25v 60 70 db output sink current isink vpin 2=2.7v,vpin 1=1.1v 2 6 ma output source current isource vpin 2=2.3v,vpin 1=5v -0.5 -0.8 ma vout high v oh vpin 2=2.3v, rl=15k ? to gnd 5 6 v vout low v ol vpin 2=2.7v,vpin 1=1.1v 0.7 1.1 v current sense section gain g v (note 3,4) 2.85 3 3.15 v/v maximum input signal v i(max) vpin 1=5v( note 3) 0.9 1 1.1 v psrr 12<=vcc<=25v 70 db input bias current i bias -2 -10 a delay to output vpin 3=0 to 2v 150 300 ns output section output low level v ol isink=20ma 0.1 0.4 v isink=200ma 1.5 2.2 v output high level v oh isource=20ma 13 13.5 v isource=200ma 12 13.5 v rise time t r tj=25 c,c l =1nf(note 2) 50 150 ns fall time t f tj=25 c,c l =1nf(note 2) 50 150 ns under-voltage lockout output section start threshold v th(st) UTC3842A 14.5 16 17.5 v utc3843a 7.8 8.4 9 v min. operating voltage v opr(min) a fter turn on UTC3842A 8.5 10 11.5 utc3843a 7 7.6 8.2 v pwm section datasheet.in
utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co., ltd. 3 qw-r103-002,b parameter symbol test conditions min typ max unit maximum duty cycle d (max) 95 97 100 % minimum duty cycle d (min) 0 % total standby current start-up current i st 0.12 0.3 ma operating supply current i cc(opr) vpin 2=vpin 3=0v 11 17 ma vcc zener voltage vz icc=25ma 34 v note 2:these parameters, although guaranteed ,are not 100% tested in production. note 3:parameters measured at trip point of latch with vpin 2=0. note 4:gain defined as: ? vpin 1 ? vpin 3 a= ; 0<=vpin3<=0.8v note 5:adjust vcc above the start threshold before setting at 15v. open-loop laboratory test fixture 1 2 8 7 3 6 4 5 a vref vcc 1k ? / 1w 0.1 f ct rt 100k ? 5k ? 4.7k ? 4.7k ? 0.1 f error amp adjust isense adjust output high peak current associated with capacity loads necessitate careful grounding techniques. timing and bypass capacitors should be connected close to pin 5 in single point gnd. the transistor and 5k ? potentio-meter are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. under-voltage lockout 7 vcc von=16v voff=10v on/off command to rest of ic von voff <1ma <15ma icc vcc during under-voltage lockout, the output driver is biased to a high impedance state. pin 6 should be shunt to gnd with a bleeder resistor to prevent activating the power switch with output leakage currents. datasheet.in
utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co. ltd 4 qw-r103-002,b error amplifier configuration 2 1 0.5ma 2.5v zf zi error amplifier can source or sink up to 0.5ma current sense circuit 5 3 1 2r r1v c rs r is error amplifier current sense comparator peak current (is) determined by the formula: ismax=10v/rs. a small rc filter be required to suppress switch transients. slope compensation 8 4 3 isense r1 r2 rsense c rt ct 0.1 f a fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converts requiring duty cycles over 50%.note that capacitor c, forms a filter with r2 to suppress the leading edge switch spikes. datasheet.in
utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co. ltd 5 qw-r103-002,b oscillator section 5 4 8 rt ct large rt small ct small rt large ct v4 v4 internal clock internal clock dead time vs c t (r t >5k ? ) timing resistance vs frequency 1 10 100 1 10 100 0.1 td ( s) ct (nf) 100 1 10 6 10 5 10 4 10 3 10 10 2 rt (k ? ) frequency (hz) ct=1nf ct=2.2nf ct=4.7nf ct=10nf ct=22nf ct=47nf ct=100nf shutdown techniques 8 3 330 ? 500 ? 1k ? 1 shutdown to current sense resistor shutdown shutdown utc uc3842a can be accomplished by two methods; either raise pin 3 above 1v or pull pin 1 below a voltage two diode drops above ground. either method caused the output of pwm comparator to be high(refer to block diagram).the pwm latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed . in one example, an externally latched shut ?down may be accomplished by adding an scr which be reset by cycling vcc below the lower uvlo threshold. a t this point the reference turns off allowing the scr to reset. datasheet.in
utc uc3842a / 3843a linear integrated circuit utc unisonic technologies co. ltd 6 qw-r103-002,b typical performance characteristics 0.01 0.1 1 0 1 2 3 4 saturation voltage (v) output current (sourse or sink current) (a) vcc=15v ta=+25c ta=-55c 7 10 3 10 6 10 5 10 4 10 10 2 10 0 20 40 60 100 80 frequency (hz) voltage gain (db) -180 -135 -90 -45 0 phase (degree) output saturation characteristics error amplifier open-loop frequency response -50 -25 0 25 50 75 100 125 150 4.96 4.97 4.98 4.99 5.00 5.01 5.02 vref (v) temperature (c) vcc=15v io=1ma -50 -25 0 25 50 75 100 125 150 250 300 350 400 450 500 550 i start (ma) temperature (c) vcc=9v -50 -25 0 25 50 75 100 125 150 9 10 11 12 13 14 15 icc (ma) temperature (c) vcc=15v io=1ma vref temperature drift istart temperature drift icc temperature drift datasheet.in
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